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| Product Flyer Mixed Signal Division MB86064 Dual 14-bit 1GSa/s DAC The Fujitsu MB86064 is a Dual 14-bit 1GSa/s digital to analog converter (DAC), delivering exceptional dynamic performance. Each high performance DAC core is capable of generating multi-standard, multi-carrier communication transmit signals, suitable for 2, 2.5 and 3G systems. DAC data is input via two high-speed LVDS ports. These operate in a pseudo double data rate (DDR) mode, with data latched on both rising and falling edges. Alternatively, the device can be configured as a multiplexed dual-port single DAC. To simplify system integration the DAC operates from a clock running at half the DAC conversion rate. October 2004 Version 1.1 FME/MS/DAC80/FL/5085 PLASTIC PACKAGE EFBGA-120 Package Dimensions 12 mm x 12 mm Features * Dual 14-bit, 1GSa/s Digital to Analog conversion * Exceptional dynamic performance * 74dBc ACLR for 4 UMTS carriers @ 276MHz direct-IF * 100MHz image-free generated bandwidth capability * supports UMTS plus digital pre-distortion bandwidth * Proprietary performance enhancement features * LVDS data interface * Register selectable on-chip LVDS termination resistors * Fujitsu 4-wire serial control interface * Two 16k point programmable on-chip waveform memories * Low power 3.3V analog and 1.8V digital operation * 750mW per DAC power dissipation at 1GSa/s * 0.18m CMOS technology with Triple Well * Performance enhanced EFBGA package * Industrial temperature range (-40C to +85C) PIN ASSIGNMENT DVDD CLK1_OUT X_CLK1_OUT X_A14 A14 DVDD X_A12 AC17 AB18 AA19 Y18 AA17 Y16 AB16 AA15 Y14 AC15 AB14 AA13 Y12 AC13 AB12 AA11 Y10 B12 X_B12 DVDD B14 X_B14 X_CLK2_OUT CLK2_OUT AC19 A12 A11 X_A10 V20 U21 T22 R23 P22 N23 M22 L23 K22 J23 H22 G23 F22 E23 E21 G21 F20 J21 H20 L21 K20 N21 M20 R21 P20 T20 AC11 AB10 AC9 AB8 AA9 Y8 AC7 AB6 AA7 Y6 AC5 AA5 B11 X_B11 DVSS B13 X_B13 X_LPCLK_IN LPCLK_IN DVSS LPCLK_OUT X_LPCLK_OUT X_A13 A13 DVSS X_A11 X_A9 A9 DVDD X_A7 A7 X_A5 A5 DVDD X_A4 A4 X_A2 A2 DVDD DVDD DVSS W23 V22 U23 W21 A10 DVSS X_A8 A8 X_A6 A6 DVSS X_A3 A3 X_A1 A1 DVSS NC NC R14 P15 N14 M15 L14 K15 J14 K13 M13 P13 R12 P11 N12 M11 L12 K11 J12 R10 P9 N10 M9 L10 K9 J10 X_B10 B10 DVSS X_B8 B8 X_B6 B6 DVSS X_B3 B3 X_B1 B1 DVSS NC NC W3 V4 U3 T4 R3 P4 N3 M4 L3 K4 J3 H4 G3 F4 E3 F2 H2 K2 M2 P2 T2 V2 W1 X_B9 B9 DVDD X_B7 B7 X_B5 B5 DVDD X_B4 B4 X_B2 B2 DVDD DVDD DVSS U1 R1 N1 L1 J1 All centre pins : TG IOUT_B AVD33 BGAP AVD18_CLK AVD25 AVD33 IOUT_A IOUTB_A D16 C17 B18 A19 A17 B16 A15 C15 B14 A13 D14 C13 B12 A11 D12 C11 B10 A9 D10 C9 B8 A7 G1 SERIAL_IN SERIAL_EN AVSS IOUTB_B AVSS DAC_SCAN SPARE D18 C19 E1 D8 C7 D6 C5 B6 A5 Applications * Multi-carrier, Multi-standard cellular infrastructure * CDMA, W-CDMA, GSM/EDGE, UMTS * Wideband communications systems * High Direct-IF architectures * Arbitrary waveform generation * Test equipment * Radar, video & display systems Copyright (c) 2004 Fujitsu Microelectronics Europe GmbH Index Not to scale. Viewed from above. VLOW_A AVD18_A AVD18_A X_RESET TEST SERIAL_OUT SERIAL_CLK AVD18_B AVD18_B VLOW_B VREF RREF AVSS CLKIN CLKINB Production Page 1 of 4 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. October 2004 Version 1.1 FME/MS/DAC80/FL/5085 MB86064 Dual 14-bit 1GSa/s DAC Functional Overview The MB86064 is a high performance Dual 14-bit 1GSa/s DAC. In addition to two DAC cores the device features a host of features designed to help both system integration and operation. A functional block diagram is shown in Figure 1. Analog performance at high frequencies is enhanced by novel current switch and switch driver designs which provide constant data-independent switching delay, reducing jitter and distortion. Control Interface 1.8V LVCMOS / 1, 2, 4, 8 / 1, 2, 4, 8 RF Clock input e.g. 500MHz Clock output 1 LVDS Clock output 2 LVDS 4-wire Serial Control Interface Port A data input 14-bit LVDS Waveform Memory Module Waveform Waveform Memory Memory A A (16K Points) (16K Points) Double-Edge clocked (1GSa/s) Loop clock input LVDS DAC A (14-bit) Analog output A Loop clock output LVDS Waveform Waveform Memory Memory B B (16K Points) (16K Points) DAC B (14-bit) Analog output B Port B data input 14-bit LVDS EFBGA-120 Figure 1 MB86064 Functional Block Diagram The device requires an input clock at half the DAC conversion rate as each DAC core is clocked on both edges of the input clock. Each DAC core can be regarded as two interleaved DACs, each running at half rate. The main reason for adopting this approach is that the switch driver inherently includes a multiplex function through its two input ports. Compared to a conventional switch driver this allows twice as long to acquire and convert, though because the two paths share current sources they match exactly at low frequencies. A characteristic of this architecture is a suppressed image appearing reflected about Fs(dac)/4 of Fclk-Fsig. Duty cycle error in the input clock will exacerbate this image, but can be minimised by trimming the differential DC offset at the clock input pins. The big advantage of this approach compared to a single DAC running at half the rate is much reduced sinx/x roll off, which gives increased output power and better in-band flatness when generating high output frequencies (e.g. 200MHz and above). This is illustrated in Figure 2 as line 1. An alternative approach using a return-to-zero output stage has the same sinx/x roll off (and switch driver speed) but 6dB lower output power and a large image at Fclk-Fout. See Line 2. Page 2 of 4 Production Copyright (c) 2004 Fujitsu Microelectronics Europe GmbH Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. October 2004 Version 1.1 FME/MS/DAC80/FL/5085 MB86064 Dual 14-bit 1GSa/s DAC Line 3 illustrates a conventional DAC running at half rate. Input Data Unsigned binary data to each DAC core is input via a dedicated parallel LVDS port. As with the DAC core, data is latched on every rising and falling edge of the clock in a pseudo DDR mode. For synchronisation of data generator(s) two LVDS clock outputs and a Loop-Clock facility are provided. dBFS 0 -6 Target high direct-IF generating region Frequency Figure 2 Benefits of DAC core architecture to Sinx/x response Loop-Clock Maintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularly taking into account device-to-device variations. The MB86064 minimises potential problems through its DDR data interface and by providing a loop-clock facility. The on-chip `loop' consists of an LVDS input connected to an LVDS output, through a programmable delay stage. This loop-through, and the associated tracking from the data generating device, should be incorporated in the feedback loop of a Delay-Locked Loop (DLL) or Phase-Locked Loop (PLL) clock generator, within the data generating device. This enables the system to compensate for variations in input/output delays in both the data generating device and the DAC. Performance Enhancement Features Each DAC core integrates a number of performance enhancing features. Performance levels now reach the level sought after for next generation systems and high direct-IF architectures. Serial Control Interface A Fujitsu 4-wire serial interface is provided for configuration and control of the DAC. Programmed data is stored in a number of read/writable registers. Waveform Memory Module The MB86064 incorporates a Waveform Memory Module featuring two 16k point on-chip waveform memories. These allow the DAC cores to be driven with user programmed waveforms without the need for external high speed, pattern generators. Development Kit A comprehensive Development Kit (DK), DK86064, is available which comprises a number of modules. A base motherboard provides an interface to the DAC, Clock and Data modules. Also included is a PC USB Interface Lead & Control Software. For further details, please refer to the associated documentation. Copyright (c) 2004 Fujitsu Microelectronics Europe GmbH Production Page 3 of 4 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. October 2004 Version 1.1 FME/MS/DAC80/FL/5085 MB86064 Dual 14-bit 1GSa/s DAC Worldwide Headquarters Japan Tel: +81 44 754 3753 Fax: +81 44 754 3329 Asia Fujitsu Limited Kamikodanaka 4-1-1 Nakahara-ku Kawasaki-shi Kanagawa-ken 211-8588 Japan Tel: +65 281 0770 Fax: +65 281 0220 Fujitsu Microelectronics Asia Pte Ltd 151 Lorong Chauan New Tech Park #05-08 Singapore 556741 http://www.fujitsu.com http://www.fmal.fujitsu.com USA Tel: +1 408 737 5600 Fax: +1 408 737 5999 Europe Fujitsu Microelectronics America, Inc. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470 USA Tel: +49 6103 6900 Fax: +49 6103 690122 Fujitsu Microelectronics Europe GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: +1 800 866 8608 Customer Response Center Fax: +1 408 737 5984 Mon-Fri: 7am-5pm (PST) http://www.fma.fujitsu.com/ http://www.fme.fujitsu.com/ 4 The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. No license is granted by implication or otherwise under any patent or patent rights of Fujitsu Microelectronics Europe GmbH. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. FME/MS/DAC80/FL/5085 1.1 Page 4 of 4 Production Copyright (c) 2004 Fujitsu Microelectronics Europe GmbH Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. |
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